1. Technical Field
The present disclosure generally relates to a method for adaptively regulating a coding mode and a digital correction circuit thereof and, more particularly, to a method for adaptively regulating a coding mode and a digital correction circuit thereof for a successive-approximation-register analog-to-digital converter (SAR ADC).
2. Description of Related Art
Conventionally, a SAR ADC uses a binary search algorithm to acquire a digital output code matched with the input analog signal. During the conversion process, the digital-to-analog converter (DAC) circuit of the SAR ADC generally adds/subtracts a binary ratio voltage to/from a reference voltage based on each of the comparison results of the comparator until the difference between the input signal and the reference voltage becomes smaller than a least significant bit (LSB) after a final required comparison cycle is completed.
However, the conversion time of the SAR ADC may vary under different process-voltage-temperature (PVT) variations. For example, if the PVT variations shorten the conversion time, the SAR ADC fails to complete the final required comparison cycle within a given time period. In other words, the actual number of completed comparison cycles is smaller than an expected value, resulting in an incorrect output result.
In view of this, there is a need for overcoming the problem of the conversion time of a SAR ADC varying due to PVT variations, in order to obtain a correct output result even with different numbers of completed comparison cycles.